Many state of the art devices require relatively planar surfaces in order to get optimum device performance. A dielectric layer may be deposited on a substrate as an insulating layer within a semiconductor die, such as between an electrically active region of the die and an electrical interconnect layer. The electrically active region may include a semiconductor transistor, a polysilicon load resistor, electrical interconnect lines, and bond pads. The dielectric layer may have a substantially nonplanar surface as deposited. The dielectric layer may be reflowed to make its surface more planar. Chemically deposited, undoped silicon dioxide needs a temperature of at least 1000.degree. C. to reflow. At 1000.degree. C., the diffusion junctions diffuse significantly further and cannot be utilized for state of the art devices requiring shallow diffusion junctions and minimal lateral diffusion.
The reflow temperature is typically dependent upon the dopant concentration within the dielectric layer. As the dopant concentration in the dielectric layer increases, the temperature at which the layer reflows decreases. Therefore, a doped dielectric layer reflows at a substantially lower temperature compared to its undoped version. Boron and phosphorus are common dopants added when depositing a silicon dioxide layer to form a borophosphosilicate glass (BPSG) layer. When the BPSG layer includes about 6.4 weight % boron and about 3.8 weight % phosphorus, the BPSG layer reflows in steam at a temperature of about 825.degree. C.
A BPSG layer having about 6.4 weight % boron and about 3.8 weight % phosphorus may delaminate during subsequent operations. When a die having the BPSG layer is assembled into a plastic package and subjected to pressure pot testing (steam at a pressure greater than atmospheric pressure), the BPSG layer may delaminate. A theory is that the steam dissolves or weakens the bonds within the BPSG layer causing the BPSG layer to delaminate. The delamination typically starts at the edge of the die and propagates towards the center of the die. If the delamination reaches an electrical interconnect, the forces within the die that cause the delamination are then applied to the electrical interconnect causing the electrical interconnect to rip apart at the weakest point in a vertical interconnect stack, typically near a contact opening, or at an interface within the electrical interconnect, such as an aluminum-silicide interface, for example. The delamination may cause other reliability problems, for instance, allowing moisture within a die's hermetic protection.
The BPSG delamination generally does not occur at lower dopant concentrations, but the BPSG layer does not significantly reflow at about 825.degree. C. in steam when the total dopant concentration is less that about 5 mole %. If a higher reflow temperature is used, the diffusion junctions or other parts of the die may be adversely affected by the high temperature.
Guard rings that are used to stop the diffusion of contaminants into an electrically active region of a die are well known in the prior art. An electrically active region may include a transistor, buried bit lines, word lines, etc. A typical prior art guard ring is formed by etching an opening through a BPSG layer and filling the opening with a metallic compound, such as aluminum, for example, to stop the contaminants. FIG. 1 shows a typical prior art guard ring. FIG. 1 includes a die 10 that has an edge 11. A guard ring 12 is near the edge 11. The guard ring is substantially parallel to the edge of the die, and each of the four sides of the guard ring generally forms four straight line segments. Within the guard ring 12 are an electrically active region 15 and bond pads 16.
Some state of art technologies requires contact openings or vias to be filled prior to depositing an interconnect layer. Problems may arise when forming the prior art guard ring that are described in reference to FIG. 2. A semiconductor substrate includes a monocrystalline silicon layer (silicon layer) 20 having a channel region 22. Over the silicon layer 20 are field oxide areas 21 that lie adjacent to the channel region 22. A patterned BPSG layer 23 includes a guard ring opening 24. During a contact or via fill process, a layer of a conductive material, such as tungsten, for example, is deposited over the substrate and etched back, thereby forming sidewall spacers 25 along the sides of the guard ring opening 24. The sidewall spacers 25 are typically very long (at least 100 .mu.m long) and may have enough force to peel away from the sides of the guard ring opening 24. A silicide layer is typically formed before the tungsten is deposited. Therefore, the spacers lie on the silicide layer. The silicide layer is removed to form a rough surface 26 during the spacer etch or a clean before depositing an electrical interconnect layer. The sidewall spacers 25 are undercut thereby forming a gap 27 between the channel region 22 and the sidewall spacers 25. Because of no mechanical support under the sidewall spacers 25, there is an increased likelihood that the sidewall spacers 25 peel from the sides of the guard ring opening 24.
Therefore, the prior art guard ring stops the BPSG layer delamination, but the guard ring formation process may cause other problems when a contact or via fill process is used. The guard ring typically has straight, long uninterrupted sides as shown in FIG. 1. Sidewall spacers may be formed along the sides of the guard ring opening when a contact hole or via filling process is used. The spacers may have enough force to peel away from the sides of the guard ring opening. If the spacers are formed over a silicide layer, the spacers may be undercut thereby increasing the probability that the spacers peel from the sides of the guard ring opening. If the spacers peel from the sides of the guard ring opening, particles, unwanted electrical shorts or reliability problems may occur.